The present invention relates to an insulated gate type semiconductor apparatus such as a power MOSFET, an IGBT (Insulated Gate Bipolar Transistor), and the like. Particularly, the invention relates to methods of realizing high-speed operation, negative gate voltage protection and prevention of a breakdown voltage drop of an insulated gate type semiconductor apparatus having a control circuit which includes an over-heating protection circuit, an over-current protection circuit, and the like on the same chip.
A technique in which an over-heating protection circuit is mounted on the same chip for improving the reliability of a power MOSFET is disclosed in Japanese Patent Application Laid-Open (JP-A) No. 7-58293. According to the conventional technique, a gate resistor is connected between an outside gate terminal and an inside gate terminal and an MOSFET for the protection circuit is connected between the inside gate terminal and an outside source terminal. When the temperature of the chip rises to a specified temperature or higher, the MOSFET for the protection circuit is turned on and a gate current flows in the resister, thereby enabling the power MOSFET to be turned off before the power MOSFET is broken.
The conventional technique relates to a self-isolation-structured device in which a control circuit is formed in a drain region of the power MOSFET in order to suppress increase of the number of processing steps. Consequently, the costs are suppressed. However, there is a problem such that when the gate voltage becomes negative, a leakage current flows from an outside drain terminal to the outside gate terminal through a parasitic npn transistor existing between the drain of the MOSFET for the protection circuit and the drain of the power MOSFET. In the conventional technique, therefore, as a countermeasure against the problem, a diode for cutting off the base current of the parasitic npn transistor is connected in series to the MOSFET for the protection circuit and, further, a diode for preventing breakdown of the above diode is connected between the outside gate terminal and the outside source terminal.
Another technique using an MOSFET in place of the gate resistor to increase the frequency of a power MOSFET having therein an over-heating protection circuit is disclosed in JP-A-6-244414. According to the conventional technique, an MOSFET in which the potential of the body is fixed to a source terminal voltage is used in place of a gate resistor between the outside gate terminal and the inside gate terminal.
In the conventional semiconductor apparatus disclosed in the above-mentioned JP-A-7-58293, a negative gate voltage protection for preventing operation of the parasitic npn transistor when the source and the drain of the MOSFET for the protection circuit are not connected to the source terminal of the power MOSFET is not considered. The conventional technique also has problems such that the power MOSFET cannot be completely turned off due to the drop of the voltage of the diode since the diode is inserted between the gate terminal and the source terminal, and the minimum gate terminal voltage for normally operating control circuits such as the over-heating protection circuit and the like cannot be decreased.
Further, in the conventional technique using the MOSFET in place of the gate resistor to realize the high-speed operation disclosed in JP-A-6-244414, it is not described that the body potential is controlled to reduce the on-resistance.
It is, therefore, a first object of the invention to provide an insulated gate type semiconductor apparatus with a control circuit having an effect of negative gate voltage protection which prevents the operation of a parasitic npn transistor when both of the source and the drain of an MOSFET for a protection circuit are not connected to the source terminal of a power MOSFET.
A second object of the invention is to provide an insulated gate type semiconductor apparatus with a control circuit, which can operate at high speed.
A third object of the invention is to provide an insulated gate type semiconductor apparatus with a control circuit, in which even when the negative gate voltage protection is achieved and the speed of the operation is increased, a drain breakdown voltage of the power MOSFET and a collector breakdown voltage of the IGBT are not dropped.
A fourth object of the invention is to provide an insulated gate type semiconductor apparatus with a control circuit in which an operation margin of the gate voltage for normally operating a control circuit part is enlarged.
In order to achieve the objects, for example, as shown in FIGS. 1 and 2, an insulated gate type semiconductor apparatus with a control circuit according to the invention comprises: a first transistor (power MOSFET 30) including a first n-type impurity region (102) on a semiconductor substrate, a second p-type impurity region (107) in contact with the first impurity region, and a third n-type impurity region (109a) covered by the second impurity region (107); a fourth p-type impurity region (104a) in contact with the first impurity region; a second transistor (MOSFET 32) including fifth and sixth impurity regions (109b, 109c) of n-type covered by the fourth impurity region; a drain terminal 1 connected to the first impurity region; a gate terminal 2 connected to the fifth impurity region (109b) of the second transistor; a source terminal 3 connected to the third impurity region; a first switch circuit (SW2) provided between the gate terminal and the fourth impurity region; and a second switch (SW3) provided between the source terminal and the fourth impurity region. In the insulated gate type semiconductor apparatus with a control circuit constructed as mentioned above, when the voltage of the gate terminal is negative relative to that of the source terminal, the second switch circuit (SW3) is turned off and the first switch circuit (SW2) is turned on. When the voltage of the gate terminal is positive relative to that of the source terminal, the second switch circuit (SW3) is turned on and the first switch circuit (SW2) is turned off. When the voltages of the gate terminal 2 and the source terminal 3 are almost equal and the voltage of the drain terminal is larger than a predetermined positive voltage relative to the voltage of the source terminal, the second switch circuit (SW3) is turned off and the first switch circuit (SW2) is turned on.
Further, as a preferable construction, as shown in the diagram, a gate electrode of the first transistor is connected to the sixth impurity region (109c) and there are also provided a third switch circuit (SW1) between the gate electrode of the first transistor and the ground (6) to which the source terminal is connected and a protection circuit (21) for detecting an overload condition of the first transistor, turning on the third switch circuit, and increasing source-drain resistance of the second transistor.
Preferably, a gate electrode of the first transistor is connected to the sixth impurity region, and there are provided: a third switch circuit (SW1) provided between the gate electrode of the first transistor and the ground (6) connected to the fourth impurity region; and a protection circuit (21) for detecting an overload condition of the first transistor, turning on the third switch circuit, and increasing source-drain resistance of the second transistor.
It is preferable that the third switch circuit (SW1) has, for example as shown in FIG. 3, a third transistor (31) which is turned on by a signal indicating that the protection circuit detects an over-heating condition of the semiconductor apparatus and a fourth transistor (42) which is turned on by a signal indicating that the protection circuit detects an over-current condition of the drain current of the first transistor.
More preferably, first and second diodes (91, 89) whose anodes are connected to the gate of the first transistor are further provided, a source-drain path of the third transistor (31) is connected between the cathode of the first diode (91) and the ground (6), and a source-drain path of the fourth transistor (42) is connected between the cathode of the second diode (89) and the ground (6).
These above and further objects and features of the invention will be seen by reference to the description, taken in connection with the accompanying drawings.